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A Seminar on Digital Design and SystemVerilog “Modern Digital Design Trends and SystemVerilog HDVL

< table> < table> A seminar titled “Modern Digital Design Trends and SystemVerilog HDVL” was held on July 19 Thursday at 3:30 pm in Room 266. It was presented by Shahriyar Masud Rizvi, Assistant Professor, Department of Electrical and Electronic Engineering, AIUB. The seminar was attended by Dr. ABM Siddique Hossain, Professor and Dean, Faculty of Engineering, Dr. Abdur Rahman, Assistant Professor and Coordinator, Faculty of Engineering, Mr. Rinku Basak, Assistant Professor and Coordinator, Faculty of Engineering, as well as Dr. Md. Abdul Mannan, Assistant Professor, Mr. Farhadur Arifin, Assistant Professor, Mr. Faisal Abrar, Lecturer, Mr. Ahmed Mortuza Saleque, Lecturer, Mr. Nafiz Ahmed Chsity, Lecturer and Mr. Kawser Marwan, Lecturer from the EEE department. It should be noted that since the development of SystemVerilog (IEEE Standard 1800) by Accellera1 in early 2000 as a Hardware Description and Verification Language (HDVL) with capabilities of both Hardware Description Languages (HDL) (such as VHSIC HDL (VHDL) and Verilog HDL) and Hardware Verification Languages (HVL) (such as e and OpeVera), SystemVerilog has gained enormous popularity in semiconductor industry and academia and has been replacing both HDLs and HVLs, especially in US semiconductor industry. Note that SystemVerilog is an IEEE standard also—IEEE standard 18002. The Electrical and Electronic Engineering department at AIUB has noted the development and increased popularity of SystemVerilog in industry and will offer 2 courses based on SystemVerilog in near future—Digital Design with Systemverilog, VHDL and FPGAs for BSc in EEE program and Computer and DSP Hardware Design with Systemverilog for the MSC in EEE program. *1 Open Verilog International (OVI) and VHDL International (VI) merged to form Accellera in early 2000. *2The VHSIC HDL (VHDL) is IEEE Standard 1076, Verilog HDL is IEEE Standard 1364 and e is IEEE standard 1647. The intended audiences of this seminar were
  1. EEE and CSE undergraduate and graduate students who are looking for entry-level Register Transfer Level (RTL) digital hardware design and verification jobs in semi-conductor industry here and abroad, 
  2. Design project/Thesis students who are planning to design or use digital controllers in their projects,
  3. EEE and CS faculties with interest in FPGA-based and ASIC-based digital design and
  4. Students enrolled in or pre-registered for VHDL Modeling and Logic Synthesis, VLSI Circuit Design, Computer System Architecture and Microprocessors courses.
Presentation covered the following Topics:
  1. Past and present trends in digital design including evolution of HDLs, FPGA and MPGA implementation fabric, High-level digital design with ESL languages (i.e. SystemC (IEEE 1666)) and Behavioral Synthesis, “Hybrid” Digital Systems—FPGAs with Soft and Hard Embedded processors, pre-defined DSP cores in FPGAs and Reconfigurable FPGAs—and techniques for complex Verification of digital circuits including Constrained Random Verification (CRV), Functional Coverage, Assertion-Based Verification (ABV) and the role of HVLs/HDVLs such as e (IEEE 1647) and SystemVerilog (IEEE 1800).
  2. Modern techniques and methodologies for Register Transfer Level digital design including EDA-based Top-down design flow that targets FPGAs and ASICs, Standards ratified by IEEE and other international bodies such as VHDL (IEEE 1076), Verilog HDL (IEEE 1364), SystemVerilog (IEEE 1800), EDIF and SDF (IEEE 1497).
  3. Hardware and Software (Design Tools) resources of VHDL Modeling and Logic Synthesis Laboratory for FPGA-based digital design. 
About the Presenter: Mr. Shahriyar Masud Rizvi is an Assistant Professor in the Department of Electrical and Electronic Engineering at AIUB. He has been teaching VHDL Modeling and Logic Synthesis course since 2003, when he joined AIUB. He has also taught VLSI Circuit Design and Control Systems. He obtained undergraduate and master’s degrees in Electrical Engineering from University of Wyoming, Laramie, WY, USA in 2000 and 2002, respectively. During graduate studies at University of Wyoming, he has worked on Verilog HDL modeling and Synthesis of implicit FSMS and EDIF processing for safe synthesis. His master’s thesis work has been published as a book by VDM-Verlag, Germany in 2011. He has published conference papers on FSM modeling and synthesis in international conferences such as Electronic Design Processes (EDP) Workshop in USA, FPGA Designer’s Forum at Southern Programmable Logic Conference (SPL) in Argentina and International Conference on Electrical and Computer Engineering (ICECE) in Bangladesh. He has developed the two SystemVerilog courses for the undergraduate and graduate EEE programs that have been mentioned above.  
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