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Comparative PVT Performance Analysis of Arithmetic Circuits in GDI and CMOS at 180nm and 45nm

Students & Supervisors

Student Authors
Sadia Tasnim Shara
Bachelor of Science in Electrical & Electronic Engineering, FE
Hamim Ibrahim
Bachelor of Science in Electrical & Electronic Engineering, FE
Supervisors
Md. Mortuza Ahmmed
Associate Professor, Faculty, FST
Dr. Shahriyar Masud Rizvi
Associate Professor, Deputy Director [dr. Anwarul Abedin Institute Of Innovation], FE

Abstract

Research Area This study combines the Electronics, VLSI and embedded systems. This paper presents a comprehensive comparative study of the Process-Voltage-Temperature performance (PVT) of key arithmetic circuits like Full Adder, 2 to 1 MUX, 2 bit Comparator in 45nm and 180 nm technology nodes for real world and critical applications. Objectives The study provides valuable design insights by comparing average power, propagation delay, leakage power, transistor count, area and process variation. The objective of this research is to compare the PVT-aware performance of arithmetic circuits implemented in CMOS and GDI at 180nm and 45nm technologies. It aims to identify the most suitable logic style and node for power-efficient, reliable operation in real-world applications like sensors, space, automotive, and mixed-signal systems. Methodology To get the analysis GDI and CMOS implementations have been used. Through post layout simulation in cadence we evaluated each design across standard PVT corners (FF,SS,TT) and temperature range from -400Cto 1250C showing their sustainability for sensors, automotive, mixed-analog signals and low cost embedded system. The analysis reveals that 45nm offer high speed and density, increased leakage, PVT sensitivity. But 180 nm circuits particularly with GDI logic, gives better thermal stability and lower leakage power which is helpful for critical environment. GDI designs reduce average power consumption by 20-40% compared to CMOS designs, without compromising speed or area. Results and Analysis The results demonstrate 180nm GDI Designs show super stability under PVT variations because it offers superior voltage tolerance, thermal stability, lower leakage and cheaper to fabricate.

Keywords

Leakage Power GDI CMOS Area

Publication Details

  • Type of Publication: Conference 
  • Conference Name: IEEE CSBDC Summer Symposium 2025
  • Date of Conference: 18/07/2025 - 18/07/2025
  • Venue: Hajee Mohammad Danesh Science and Technology University (HSTU), Dinajpur
  • Organizer: IEEE Computer Society Bangladesh Chapter
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